1. Field of the Invention
This invention relates to frequency-variation type demodulator and demodulating method, and more particularly, to a method to enhance operation speed and to reduce chip complexity applied to frequency-converting type demodulator and demodulating method.
2. Description of Related Prior Art
In the medical application, the ultrasonic inspection for a child conceived in a mother-to-be or for organs in human body has been widely applied. As the ultrasonic signal is propagating within the human organs, the central frequency of the ultrasonic is varied according to the transmitting depth within the organ. Thus, a required frequency is generated using a frequency-converting type demodulator.
FIG. 1A is a diagram showing the relationship between the frequency and time. FIG. 1B is a diagram showing another relationship between frequency and time. In FIG. 1A, Fstart represents a start frequency and Fslope represents the slope of the frequency variation. The value of the frequency variation slope can be positive or negative. For example, in FIG. 1B, Fupslope is a positive value, while Fdownslope is a negative value. In FIG. 1A, the magnitudes of Fstart and Fslope are calculated from mathematical algorithm. The factors that affect Fstart and Fslope include the attenuation coefficient of ultrasonic generated via traveling through different organs, and the transmitting depth within such organs. Fstart and Fslope are used as input parameters provided for the demodulator. The detailed description is not illustrated here.
FIG. 2 shows a block diagram of a conventional demodulator. ƒp(t) represents a transient phase demodulating frequency, ƒD(t) represents a demodulating frequency profile, tprepresents the demodulating reference time, and t-TBREAK is the time index after a turning frequency of the demodulating frequency. For example, in FIG. 1B, FBREAK is the break frequency of demodulating frequency, tR is the residue time, ƒPC(t) is the phase correction value, ƒDV(t) is the demodulating phase value, and ejxcfx86 is the phaser value.
When a demodulating frequency is applied from a data input to a phase and frequency processor 200, it is received via a frequency profile generator 202 in the phase and frequency processor 200. Meanwhile, the demodulating frequency is operated by mathematical algorithm to obtain the demodulating frequency profile ƒp(t) and the transient phase demodulating frequency ƒD(t).
A multiplication operation is performed on the demodulating frequency profile ƒp(t) and the demodulating reference time tD in the first multiplier 204. The result obtained from the multiplication is then added with a constant in the first adder 212. The result after the addition in the first adder 212 is the demodulating phase value ƒDV(t). In FIG. 1B, when the demodulating reference time tD is less than the break time TBREAK, the demodulating reference time tD is output from a first multiplexer 208 to the first multiplier 204, while a constant of xe2x80x9c0xe2x80x9d is output from the second multiplexer 210 to the first adder 212. Meanwhile, the demodulating phase value is ƒDV(t)=ƒD(t)xc2x7tD. If the demodulating reference time tD is greater than the break time TBREAK, the first multiplexer 208 outputs a demodulating reference time tDxe2x88x92TBREAK to the first multiplier 204, and the second multiplexer 210 outputs a constant ƒD(TBREAK)xc2x7TBREAK. Meanwhile, the demodulating phase is ƒDV(t)=ƒD(t)xc2x7(tDxe2x88x92TBREAK)+ƒD(TBREAK)xc2x7TBREAK.
A multiplication operation is performed on the transient phase demodulating frequency ƒp(t) and the residue time tR in the second multiplier 206. The result for the multiplication operation is the phase correction value ƒPC(t). An addition operation is performed on the demodulating phase value ƒDV(t) and the phase correction value ƒPC(t) in the second adder 214. The added value is the phase value xcfx86.
Sine value and cosine value are built in a look-up table 216. When the phase value xcfx86 is input to the look-up table 216, a sine value and a cosine value corresponding to the input phase value xcfx86 are generated. A measured digital signal is input to a third multiplier 218 at DataIn, and a multiplication operation is performed with the sine of the phase value xcfx86, to obtain a quadrature-phase demodulating signal. The quadrature-phase demodulating signal is output to a subordinative circuit at OUTPUT. Similarly, a multiplication operation is performed on the measured digital signal and the cosine of the phase value xcfx86 to produce in an in-phase demodulating signal which is output to the subordinative circuit at OUTPUT.
The conventional demodulator requires a lot of multipliers for performing multiplication. When the digit number of the multiplier is large, the frequency is time varying and the multiplication has to be performed with a high speed operation clock, the operation of the demodulation cannot be achieved under the current technique. If the above method is to be implemented via hardware, there is a great difficulty in fabrication of integrated circuit.
The invention provides frequency-variation type demodulator and demodulating method. A pipeline technique is used to reduce the computation load by addition or subtraction operation only. That is, adders or subtractors are used to replace the multipliers used in the conventional demodulator and demodulating method.
The demodulating method comprises the following steps. An initial value is received and delayed with a delay time to generate a control signal. The control signal, a start frequency, a frequency variation slope and a clock are provided to obtain a phase value via mathematical calculation. According to the phase value, a corresponding sine value and a corresponding cosine value are obtained from a look-up table. A digital signal is measured, then a multiplication operation is performed on the measured digital signal and the cosine value to obtain an in-phase demodulating signal. A multiplication operation is further performed on the measured digital signal and the sine value to obtain an out-of-phase demodulating phase.
In the demodulating method provided by the invention, the method for obtaining the phase value comprises the following steps. A parameter input value and a parameter address value are received. The parameter input value is allocated to obtain a start frequency and a frequency variation slope. A subtraction operation is performed on the start frequency and frequency variation slope to obtain the first differential.
A binary digit shift is performed on the frequency variation slope to obtain a shift value. An accumulated digit shift value, the digit shift value, the control signal and the clock are received to be performed with an addition operation, so that the updated accumulated digit shift value is obtained.
The first differential, the updated accumulated digit shift value, the control signal and the clock are received, and a subtraction operation is performed on the first differential and the updated accumulated digit shift value to obtain a second differential. The phase value obtain from the previous addition operation, the control signal, the second differential and the clock are received. An addition operation is performed on the phase value obtained from the previous addition operation and the second differential to obtain the phase value.
In the demodulator provided by the invention, a control signal apparatus comprises an input terminal and an output terminal. The input terminal receives the start signal, while the control signal is sent out from the output terminal after a delay time. An in-phase and quadrature-phase function generator comprises a first input terminal coupled to the output of the control signal apparatus to receive the control signal. The in-phase and quadrature-phase function generator further comprises a second input terminal to receive the start frequency, a third input terminal to receive the frequency variation slope and a fourth input terminal to receive the clock. Using mathematical calculation, a phase value can be derived at an output terminal.
The demodulator comprises a first and a second read only memory units and each of which includes an input terminal and an output terminal. The input terminals of the first and the second ROM units are coupled to the output terminal of the in-phase and quadrature-phase function generator to receive the phase value. According to the phase value, a corresponding cosine function value and a sine function value can be obtained from the cosine and sine function look-up tables in the first and the second ROM units. The output terminals of the first and second ROM units then output the cosine function value and the sine function value, respectively.
The first multiplier comprises a first input terminal to receive a measured digital data, a second input terminal coupled to the output terminal of the first ROM unit to receive the cosine value. A multiplication operation is performed on the measured digital data and the cosine value to obtain an in-phase demodulating signal which is output by the output terminal of the first multiplier. The second multiplier comprises a first input terminal to receive the measured digital data, a second input terminal coupled to the output of the second ROM unit to receive the sine value. The measured digital data is multiplied by the sine value within the second multiplier, so that a quadrature-phase demodulating signal is obtained at the output terminal of the second multiplier.
In another embodiment of the invention, a frequency-variation type digital demodulator is provided to comprise an in-phase and quadrature-phase function generator, a first and second subtractors, a shifter, and a first and second adders. The in-phase and quadrature-phase function generator comprises a parameter decoder. The parameter decoder comprises a first input terminal to receive a parameter input value and a second input terminal to receive a parameter address value. According to the parameter address value received at the second input terminal, the parameter input value is allocated. When the parameter input value is the start frequency, a first output terminal thereof outputs the start frequency. When the parameter input value is the frequency variation slope, the second output terminal thereof outputs the frequency variation slope.
The first subtractor comprises a first input terminal coupled to the first output terminal of the parameter decoder to receive the start frequency, and a second input terminal coupled to the second output terminal of the parameter decoder to receive the frequency variation slope. A subtraction operation is performed on the received start frequency and the frequency variation slope to obtain a first differential output by an output terminal of the first subtractor.
The shifter comprises an input terminal coupled to the second output terminal of the parameter decoder to receive the frequency variation slope. The frequency variation slope is shifted according to binary digit logic to obtain a phase shift value output by an output terminal of the shifter.
The first adder comprises four input terminals and an output terminal. The first input terminal is coupled to the output terminal of the first adder to receive a feedback of the accumulated added phase shift value obtained by a previous calculation. The second input terminal is coupled to the output terminal of the shifter to receive the phase shift value. The third input terminal is to receive the control signal, while the fourth input terminal is to receive the clock. The accumulation added phase shift value calculated by the previous addition operation is added with the phase shift value to obtain the accumulative added phase shift value which is then output to the output terminal.
The second subtractor comprises four input terminals and one output terminal. The first input terminal is coupled to the output terminal of the first subtractor to receive the first differential. The second input terminal is coupled to the output of the shifter to receive the accumulated phase shift value, the third input terminal is to receive the control signal, and the fourth input terminal is to receive the clock. The first differential and the accumulated phase shift value is subtracted with each other to obtain a second differential. The second differential is sent out to the output terminal.
The second adder comprises four input terminals and one output terminal. The first input terminal is coupled to the output of the second adder to receive the feedback of the phase value obtained by the previous addition operation. The second input terminal is coupled to the output terminal to receive the second differential. The third input terminal is to receive the control signal, and the fourth input terminal is to receive the clock. The phase value obtained from the previous addition operation and the second differential are added with each other to obtain a phase value output from the output terminal of the second adder.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.